SH7616 datasheet(17/935 Pages) RENESAS

17 / 935 page

Rev. 2.00 Mar 09, 2006 page xvii of xxvi

Section 8 Cache.................................................................................................................... 357

8.1

Introduction....................................................................................................................... 357

8.1.1

8.2

Register Description.......................................................................................................... 358

8.2.1

Cache Control Register (CCR)............................................................................. 358

8.3

Address Space and the Cache............................................................................................ 360

8.4

Cache Operation................................................................................................................ 361

8.4.1

Cache Reads......................................................................................................... 361

8.4.2

Write Access ........................................................................................................ 363

8.4.3

Cache-Through Access ........................................................................................ 366

8.4.4

The TAS Instruction............................................................................................. 366

8.4.5

Pseudo-LRU and Cache Replacement ................................................................. 366

8.4.6

Cache Initialization .............................................................................................. 368

8.4.7

Associative Purges ............................................................................................... 368

8.4.8

Cache Flushing..................................................................................................... 369

8.4.9

Data Array Access ............................................................................................... 369

8.4.10 Address Array Access.......................................................................................... 370

8.5

Cache Use ......................................................................................................................... 371

8.5.1

Initialization ......................................................................................................... 371

8.5.2

Purge of Specific Lines ........................................................................................ 372

8.5.3

Cache Data Coherency......................................................................................... 372

8.5.4

Two-Way Cache Mode ........................................................................................ 373

8.6

Usage Notes ...................................................................................................................... 374

8.6.1

Standby ................................................................................................................ 374

8.6.2

Cache Control Register ........................................................................................ 374

Section 9 Ethernet Controller (EtherC)......................................................................... 375

9.1

Overview........................................................................................................................... 375

9.1.1

Features................................................................................................................ 375

9.1.2

Configuration ....................................................................................................... 376

9.1.3

Pin Configuration................................................................................................. 378

9.1.4

Ethernet Controller Register Configuration ......................................................... 379

9.2

Register Descriptions ........................................................................................................ 380

9.2.1

EtherC Mode Register (ECMR)........................................................................... 380

9.2.2

EtherC Status Register (ECSR)............................................................................ 383

9.2.3

EtherC Interrupt Permission Register (ECSIPR) ................................................. 384

9.2.4

PHY Interface Register (PIR) .............................................................................. 385

9.2.5

MAC Address High Register (MAHR)................................................................ 386

9.2.6

MAC Address Low Register (MALR)................................................................. 387

9.2.7

Receive Frame Length Register (RFLR) ............................................................. 388

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