SH7616 datasheet(70/935 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 44 of 906

REJ09B0292-0200

2.2.5

DSP Type Instructions and Data Formats

The DSP data format and valid data length are determined by DSP type instructions and DSP

registers. There are three types of instructions that access DSP data registers, DSP data processing,

X, Y data transfer processing, and single data transfer processing instructions.

DSP Data Processing: The guard bits (bits 39–32) are valid when the A0 and A1 registers are

used as source registers in DSP fixed-point data processing. When any registers other than A0, A1

(e.i., M0, M1, X0, X1, Y0, Y1 registers) are used as source registers, the sign-extended part of that

registers, the guard bits (bits 39–32) are valid. When any registers other than A0, A1 are used as

destination registers, bits 39 to 32 of the result data are disregarded.

Processing for DSP integer data is the same as the DSP fixed-point data processing. However, the

lower word (the lower 16 bits, bits 15–0) of the source register is disregarded. The lower word of

the destination register is cleared to 0.

In DSP logical data processing, the upper word (the upper 16 bits, bits 31–16) of the source

upper word of the destination register is valid. The lower word and the guard bits of the A0, A1

registers are cleared to 0.

X, Y Data Transfers: The MOVX.W and MOVY.W instructions access X, Y memory via the

16-bit X, Y data buses. The data loaded into registers and data stored from registers is always the

upper word (the upper 16 bits, bits 31–16).

When loading, the MOVX.W instruction loads X memory, with the X0 and X1 registers as the

destination registers. The MOVY.W instruction loads Y memory, with the Y0 and Y1 registers as

the destination registers. Data is stored in the upper word of the register; the lower word is cleared

to 0.

The upper word data of the A0, A1 registers can be stored in X or Y memory with these data

transfer instructions, but storing is not possible from any other registers. The guard bits and the

lower word of the A0, A1 registers are disregarded.

Single Data Transfers: The MOVS.W and MOVS.L instructions can access any memory via the

data bus (CDB). All DSP registers are connected to the CDB bus, and they can become source or

destination registers during data transfers. The two data transfer modes are word and longword.

In word mode, data is loaded to and stored in the upper word of the DSP register, with the

exception of the A0G, A1G registers. In longword mode, data is loaded to and stored in the 32 bits

of the DSP register, with the exception of the A0G, A1G registers. The A0G, A1G registers can be

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