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SH7616 Datasheet(PDF) 67 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 67 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Mar 09, 2006 page 41 of 906
REJ09B0292-0200
2.2
Data Formats
2.2.1
Data Format in Registers
Register operand data size is always longword (32 bits). When loading data from memory into a
register, if the memory operand is a byte (8 bits) or a word (16 bits), it is sign-extended into a
longword, then loaded into the register.
31
0
Longword
Figure 2.5 Register Data Format
2.2.2
Data Formats in Memory
These formats are classified into bytes, words, and longwords.
Place byte data in any address, word data from 2n addresses, and longword data from 4n
addresses. An address error will occur if accesses are made from any other boundary. In such
cases, the access results cannot be guaranteed. In particular, the stack area referred to by the
hardware stack pointer (SP, R15) stores the program counter (PC) and status register (SR) as
longwords, so establish the hardware stack pointer so that a 4n value will always result.
To enable sharing of the processor accessing memory in little-endian mode and memory, the CS2,
4 space (area 2, 4) has a function that allows access in little-endian mode. The order of byte data
differs between little-endian mode and normal big-endian mode.
31
0
15
23
7
Byte
Byte
Byte
Byte
Word
Word
Address 2n
Address 4n
Longword
Address m
Address m + 2
Address m + 1
Address m + 3
Big endian
31
0
15
23
7
Byte
Byte
Byte
Byte
Word
Word
Address 2n
Address 4n
Longword
Address m + 3
Address m + 1
Address m + 2
Address m
Little endian
Figure 2.6 Data Formats in Memory



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