SH7616 datasheet(36/935 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 10 of 906

REJ09B0292-0200

Item

Specifications

User debug

interface (H-UDI)

• Conforms to IEEE1149.1 standard

 Five test signals (TCK, TDI, TDO, TMS, TRST)

 TAP controller

 Instruction register

 Data register

 Bypass register

• Test mode that conforms to the IEEE1149.1 standard

 Standard instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST

 Optional instructions: CLAMP, HIGHZ, and IDCODE

• H-UDI interrupt

 H-UDI interrupt request to INTC

• Reset hold

Timer pulse unit

(TPU), 3 channels

• Maximum 8-pulse input/output

• Total of eight timer general registers (TGR) (four for channel 0, two each

for channels 1 and 2)

 Waveform output by compare match: Selection of 0, 1, or toggle output

 Input capture function: Selection of rising-edge, falling-edge, or both-

edge detection

 Counter clear operation: Counter clearing possible by compare match

or input capture

 Synchronous operation: Multiple timer counters (TCNT) can be written

to simultaneously; simultaneous clearing by compare match and input

capture possible; simultaneous register input/output possible by

counter synchronous operation

 PWM mode: Any PWM output duty can be set; maximum 7-phase

PWM output possible by combination with synchronous operation

• Buffer operation settable for channel 0

 Input capture register double-buffering possible

 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for channels 1 and 2

 Two-phase encoder pulse up/down-count possible

• 13 interrupt sources

 For channel 0, four compare match/input capture dual-function

interrupts and one overflow interrupt can be requested independently

 For channels 1 and 2, two compare match/input capture dual-function

interrupts, one overflow interrupt, and one underflow interrupt can be

requested independently

SH7616 Datasheet(PDF) 36 Page - Renesas Technology Corp

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