SH7616 datasheet(62/935 Pages) RENESAS

62 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 36 of 906

REJ09B0292-0200

There are dedicated load/store instructions for accessing the RS, RE and MOD registers. For

example, the RS register is accessed as follows.

LDC

Rm,RS;

→RS

LDC.L

@Rm+,RS;

(Rm)

→RS,Rm+4→Rm

STC

RS,Rn;

→Rn

STC.L

RS,@-Rn;

Rn-4

→Rn,RS→(Rn)

The following instructions set addresses in the RS, RE registers for zero overhead repeat control:

LDRS

@(disp,PC);

disp

×2 + PC→RS

LDRE

@(disp,PC);

disp

×2 + PC→RE

The GBR register and VBR register are the same as the previous SuperH microprocessor registers.

An RC counter and four control bits (DMX bit, DMY bit, RF1 bit, RF0 bit) have been added to

the SR register. The RS, RE and MOD registers are new registers.

2.1.3

System Registers

System registers consist of four 32-bit registers: high and low multiply and accumulate registers

(MACH and MACL), the procedure register (PR), and the program counter (PC). The MACH and

MACL store the results of multiplication or multiply and accumulate operations*. The PR stores

the return address from the subroutine procedure. The PC indicates the address of the program in

execution; it controls the flow of the processing. The PC indicates the fourth byte after the

instruction currently being executed. These registers are the same as those in the SuperH

microprocessor.

Note: These are used only when executing an instruction that was supported by SH-1 and SH-2.

They are not used for newly added multiplication instructions (PMULS).

MACL

MACH

Multiply and accumulate

Procedure register (PR)

Program counter (PC)

Figure 2.3 System Register Configuration

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