SH7616 datasheet(53/935 Pages) RENESAS

53 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 27 of 906

REJ09B0292-0200

When used for general input/output, attention must be paid to the polarity of

this pin.

1.4

Processing States

State Transitions: The CPU has five processing states: the reset state, exception handling state,

bus-released state, program execution state, and power-down state. Figure 1.3 shows the state

transitions.

RST = 0, NMI = 1

RST = 1,

NMI = 0

RST = 1,

NMI = 1

Interrupt or DMA

address error

NMI interrupt

End of

exception

handling

Bus

request

Exception

Bus request

cleared

Bus request

received

Bus request

cleared

SLEEP

instruction

(SBY = 0)

SLEEP

instruction

(SBY = 1)

From any state when

RES = 0 and NMI = 1

From any state when

RES = 0 and NMI = 0

Reset states

Power-down state

Note: * clock pause function

Bus request

received

Bus request

cleared

RST = 0, NMI = 0

MSTP

bit

cleared

MSTP

bit set

Bus-released state

Exception-handling state

Manual reset state

Power-on reset state

Program execution state

Sleep mode

Standby mode

Module standby

SBY bit set and

CKPREQ = 0*

CKPREQ = 1*

Figure 1.3 Processing State Transitions

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