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SH7616 Datasheet(PDF) 14 Page - Renesas Technology Corp |
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SH7616 Datasheet(HTML) 14 Page - Renesas Technology Corp |
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14 / 935 page ![]() Rev. 2.00 Mar 09, 2006 page xiv of xxvi 5.3.18 Vector Number Setting Register L (VCRL) ........................................................ 175 5.3.19 Vector Number Setting Register M (VCRM) ...................................................... 176 5.3.20 Vector Number Setting Register N (VCRN)........................................................ 177 5.3.21 Vector Number Setting Register O (VCRO)........................................................ 178 5.3.22 Vector Number Setting Register P (VCRP)......................................................... 179 5.3.23 Vector Number Setting Register Q (VCRQ)........................................................ 180 5.3.24 Vector Number Setting Register R (VCRR) ........................................................ 181 5.3.25 Vector Number Setting Register S (VCRS)......................................................... 182 5.3.26 Vector Number Setting Register T (VCRT) ........................................................ 183 5.3.27 Vector Number Setting Register U (VCRU)........................................................ 184 5.3.28 Interrupt Control Register (ICR).......................................................................... 187 5.3.29 IRQ Control/Status Register (IRQCSR) .............................................................. 188 5.4 Interrupt Operation............................................................................................................ 190 5.4.1 Interrupt Sequence ............................................................................................... 190 5.4.2 Stack State after Interrupt Exception Handling.................................................... 192 5.5 Interrupt Response Time................................................................................................... 192 5.6 Sampling of Pins IRL3–IRL0 ........................................................................................... 194 5.7 Usage Notes ...................................................................................................................... 195 Section 6 User Break Controller (UBC) ....................................................................... 199 6.1 Overview........................................................................................................................... 199 6.1.1 Features................................................................................................................ 199 6.1.2 Block Diagram..................................................................................................... 200 6.1.3 Register Configuration......................................................................................... 201 6.2 Register Descriptions ........................................................................................................ 203 6.2.1 Break Address Register A (BARA) ..................................................................... 203 6.2.2 Break Address Mask Register A (BAMRA)........................................................ 204 6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 205 6.2.4 Break Address Register B (BARB) ..................................................................... 207 6.2.5 Break Address Mask Register B (BAMRB) ........................................................ 208 6.2.6 Break Bus Cycle Register B (BBRB) .................................................................. 209 6.2.7 Break Address Register C (BARC)...................................................................... 211 6.2.8 Break Address Mask Register C (BAMRC) ........................................................ 212 6.2.9 Break Data Register C (BDRC) ........................................................................... 214 6.2.10 Break Data Mask Register C (BDMRC).............................................................. 215 6.2.11 Break Bus Cycle Register C (BBRC) .................................................................. 217 6.2.12 Break Execution Times Register C (BETRC) ..................................................... 218 6.2.13 Break Address Register D (BARD) ..................................................................... 219 6.2.14 Break Address Mask Register D (BAMRD)........................................................ 220 6.2.15 Break Data Register D (BDRD)........................................................................... 222 |
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