SH7616 datasheet(13/935 Pages) RENESAS

13 / 935 page

Rev. 2.00 Mar 09, 2006 page xiii of xxvi

4.6.3

Instructions in Repeat Loops................................................................................ 140

4.7

Stack Status after Exception Handling.............................................................................. 141

4.8

Usage Notes ...................................................................................................................... 142

4.8.1

Value of Stack Pointer (SP) ................................................................................. 142

4.8.2

Value of Vector Base Register (VBR) ................................................................. 142

4.8.3

Address Errors Caused by Stacking of Address Error Exception Handling ........ 142

4.8.4

Manual Reset during Register Access.................................................................. 142

Section 5 Interrupt Controller (INTC)........................................................................... 143

5.1

Overview........................................................................................................................... 143

5.1.1

Features................................................................................................................ 143

5.1.2

Block Diagram ..................................................................................................... 143

5.1.3

Pin Configuration................................................................................................. 145

5.1.4

5.2

Interrupt Sources ............................................................................................................... 146

5.2.1

NMI Interrupt....................................................................................................... 147

5.2.2

User Break Interrupt............................................................................................. 147

5.2.3

H-UDI Interrupt ................................................................................................... 147

5.2.4

IRL Interrupts....................................................................................................... 147

5.2.5

IRQ Interrupts ...................................................................................................... 148

5.2.6

On-chip Peripheral Module Interrupts ................................................................. 152

5.2.7

Interrupt Exception Vectors and Priority Order ................................................... 152

5.3

Register Descriptions ........................................................................................................ 159

5.3.1

Interrupt Priority Level Setting Register A (IPRA) ............................................. 159

5.3.2

Interrupt Priority Level Setting Register B (IPRB).............................................. 160

5.3.3

Interrupt Priority Level Setting Register C (IPRC).............................................. 161

5.3.4

Interrupt Priority Level Setting Register D (IPRD) ............................................. 162

5.3.5

Interrupt Priority Level Setting Register E (IPRE) .............................................. 163

5.3.6

Vector Number Setting Register WDT (VCRWDT) ........................................... 164

5.3.7

Vector Number Setting Register A (VCRA)........................................................ 165

5.3.8

Vector Number Setting Register B (VCRB) ........................................................ 166

5.3.9

Vector Number Setting Register C (VCRC) ........................................................ 166

5.3.10 Vector Number Setting Register D (VCRD)........................................................ 167

5.3.11 Vector Number Setting Register E (VCRE) ........................................................ 168

5.3.12 Vector Number Setting Register F (VCRF)......................................................... 169

5.3.13 Vector Number Setting Register G (VCRG)........................................................ 170

5.3.14 Vector Number Setting Register H (VCRH)........................................................ 171

5.3.15 Vector Number Setting Register I (VCRI)........................................................... 172

5.3.16 Vector Number Setting Register J (VCRJ) .......................................................... 173

5.3.17 Vector Number Setting Register K (VCRK)........................................................ 174

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