SH7616 datasheet(76/935 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 50 of 906

REJ09B0292-0200

T Bit: The T bit in the status register (SR) changes according to the result of a comparison, and

conditional branches occur in accordance with its true or false status. The number of instructions

modifying the T bit is kept to a minimum to improve the processing speed.

Table 2.8

T Bit

SH7616 CPU

Description

Example of Conventional CPU

CMP/GE R1,R0

TRGET0

TRGET1

T bit is set when R0

≥ R1.

The program branches to TRGET0

when R0

≥ R1.

The program branches to TRGET1

when R0 < R1

CMP.W R1,R0

BGE

TRGET0

BLT

TRGET1

ADD

#–1,R0

CMP/EQ #0,R0

TRGET

T bit is not changed by ADD. T bit

is set when R0 = 0. The program

branches when R0 = 0

SUB.W #1,R0

BEQ

TRGET

Immediate Data: Byte immediate data resides in instruction code. Word or longword immediate

data is not input in instruction codes but is stored in a memory table. An immediate data transfer

instruction (MOV) accesses the memory table using the PC relative addressing mode with

displacement.

Table 2.9

Immediate Data Accessing

Classification

SH7616 CPU

Example of Conventional CPU

8-bit immediate

MOV

#H'12,R0

MOV.B

#H'12,R0

16-bit immediate

MOV.W @(disp,PC),R0

........

.DATA.W H'1234

MOV.W #H'1234,R0

32-bit immediate

MOV.L

@(disp,PC),R0

........

.DATA.L H'12345678

MOV.L

#H'12345678,R0

Note: @(disp, PC) accesses the immediate data.

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