SH7616 datasheet(74/935 Pages) RENESAS

Part #	SH7616

Description	32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series

PDF	935 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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74 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 48 of 906

REJ09B0292-0200

A0G

A1G

DSR

CDB

XDB

YDB

MOVS.W,

MOVS.L

32 bits

16 bits

32 bits

MOVX.W,

MOVY.W

MOVS.W,

MOVS.L

8 bits

[7:0]

Figure 2.8 DSP Register-Bus Relationship during Data Transfers

2.3

CPU Core Instruction Features

The CPU core instructions are RISC type. The characteristics are as follows.

16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.

One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using

the pipeline system. One state equals 16.0 ns when operating at 62.5 MHz.

Data Length: Longword is the basic data length for all operations. Memory can be accessed in

bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and

handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-

extended for logic operations. It also is handled as longword data.

SH7616 Datasheet(PDF) 74 Page - Renesas Technology Corp