SH7616 datasheet(75/935 Pages) RENESAS

75 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 49 of 906

REJ09B0292-0200

Table 2.6

Sign Extension of Word Data

SH7616 CPU

Description

Example of Conventional CPU

MOV.W

@(disp,PC),R1

ADD

R1,R0

........

.DATA.W H'1234

Data is sign-extended to 32

bits, and R1 becomes

H'00001234. It is next operated

upon by an ADD instruction

ADD.W

#H'1234,R0

Note: @(disp, PC) accesses the immediate data.

Load-Store Architecture: Basic operations are executed between registers. For operations that

involve memory access, data is loaded to the registers and executed (load-store architecture).

However, Instructions such as AND manipulating bits, are executed directly in memory.

Delayed Branches: Such instructions as unconditional branches are delayed branch instructions.

In the case of delayed branch instructions, the branch occurs after execution of the instruction

immediately following the delayed branch instruction (slot instruction). This reduces pipeline

disruption during branching.

The branching operation of the delayed branch occurs after execution of the slot instruction.

However, with the exception of such branch operations as register updating, execution of

instructions is performed with the order of delayed branch instruction, then delayed slot

instruction.

For example, even if the contents of a register storing a branch destination address are modified by

a delayed slot, the branch destination address will still be the contents of the register before the

modification.

Table 2.7

Delayed Branch Instructions

SH7616 CPU

Description

Example of Conventional CPU

BRA

TRGET

ADD

R1,R0

Executes an ADD before

branching to TRGET

ADD.W

R1,R0

BRA

TRGET

Multiplication/Multiply-Accumulate Operation: 16

× 16 → 32 multiplications execute in one

to three cycles, and 16

× 16 + 64 → 64 multiply-accumulate operations execute in two to three

cycles. 32

× 32 → 64 multiplications and 32 × 32 + 64 → 64 multiply-accumulate operations

execute in two to four cycles.

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