SH7616 datasheet(33/935 Pages) RENESAS

33 / 935 page

Section 1 Overview

Rev. 2.00 Mar 09, 2006 page 7 of 906

REJ09B0292-0200

Item

Specifications

Direct memory

access controller

(DMAC),

2 channels

• 4-Gbyte address space, maximum 16M (16,777,216) transfers

• Selection of 8-bit, 16-bit, 32-bit, or 16-byte transfer data length

• Parallel execution of CPU instruction processing and DMA operation

possible in case of cache hit

• Selection of dual address or single address mode

 Single address (data transfer rate of one transfer unit in one bus cycle)

 Dual address (data transfer rate of one transfer unit in two bus cycles)

 When synchronous DRAM is connected, 16-byte continuous read →

continuous write transfer is possible (dual)

• When SDRAM is connected, clocked single-address transfer is possible at

rates up to 31.25 MHz

• Cycle stealing or burst transfer

• Relative channel priorities can be set (fixed mode/round robin mode)

• DMA transfer is possible for the following devices:

 External memory, on-chip memory, on-chip supporting modules

(excluding DMAC, BSC, UBC, cache, E-DMAC, EtherC)

• External requests, DMA transfer requests from on-chip supporting

modules, auto requests

• Interrupt request (DEIn) can be issued to CPU at end of data transfer

• DACK used for DREQ sampling (however, there is always one overrun as

there is one acceptance before first DACK)

On-chip RAM

• 4-kbyte X-RAM

• 4-kbyte Y-RAM

Ethernet controller

direct memory

access controller

(E-DMAC),

2 channels

• Transfer possible between EtherC and external memory/on-chip memory

• 16-byte burst transfer possible

• Single address transfer

• Chain block transfer

• 32-bit transfer data width

• 4-Gbyte address space

• Data transfer possible from across byte boundaries in transmission

• Each transmit and receive FIFO includes 2 kbytes

SH7616 Datasheet(PDF) 33 Page - Renesas Technology Corp

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