SH7616 datasheet(16/935 Pages) RENESAS

16 / 935 page

Rev. 2.00 Mar 09, 2006 page xvi of xxvi

7.4.1

Basic Timing........................................................................................................ 282

7.4.2

Wait State Control................................................................................................ 287

7.4.3

CS Assertion Period Extension............................................................................ 291

7.5

Synchronous DRAM Interface.......................................................................................... 292

7.5.1

Synchronous DRAM Direct Connection ............................................................. 292

7.5.2

Address Multiplexing........................................................................................... 294

7.5.3

Burst Reads .......................................................................................................... 296

7.5.4

Single Reads ........................................................................................................ 301

7.5.5

Single Writes........................................................................................................ 303

7.5.6

Burst Write Mode ................................................................................................ 304

7.5.7

Bank Active Function .......................................................................................... 306

7.5.8

Refreshes.............................................................................................................. 317

7.5.9

Overlap Between Auto Precharge Cycle (Tap) and Next Access ........................ 320

7.5.10 Power-On Sequence............................................................................................. 321

7.5.11 64 Mbit Synchronous DRAM (2 Mword

× 32-bit) Connection........................... 323

7.6

DRAM Interface ............................................................................................................... 324

7.6.1

DRAM Direct Connection ................................................................................... 324

7.6.2

Address Multiplexing........................................................................................... 325

7.6.3

Basic Timing........................................................................................................ 326

7.6.4

Wait State Control................................................................................................ 327

7.6.5

Burst Access ........................................................................................................ 329

7.6.6

EDO Mode........................................................................................................... 332

7.6.7

DRAM Single Transfer........................................................................................ 336

7.6.8

Refreshing............................................................................................................ 337

7.6.9

Power-On Sequence............................................................................................. 339

7.7

Burst ROM Interface......................................................................................................... 339

7.8

Idles between Cycles......................................................................................................... 343

7.9

Bus Arbitration.................................................................................................................. 345

7.9.1

Master Mode........................................................................................................ 349

7.10 Additional Items................................................................................................................ 350

7.10.1 Resets................................................................................................................... 350

7.10.2 Access as Viewed from CPU, DMAC or E-DMAC ............................................ 351

7.10.3 STATS1 and STATS0 Pins ................................................................................. 352

7.10.4

BUSHiZ Specification ......................................................................................... 353

7.11 Usage Notes ...................................................................................................................... 354

7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC..... 354

7.11.2 When Using I

φ: Eφ Clock Ratio of 1: 1, 8-Bit Bus Width,

and External Wait Input ....................................................................................... 356

7.11.3 When connecting external device to synchronous DRAM .................................. 356

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