SH7616 datasheet(71/935 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 45 of 906

REJ09B0292-0200

treated as independent registers during single data transfers. The load/store data length for the

A0G, A1G registers is 8 bits.

If DSP registers are used as source registers in word mode, when data is stored from any registers

other than A0G, A1G, the data in the upper word of the register is transferred. In the case of the

A0, A1 registers, the guard bits are disregarded. When the A0G, A1G registers are the source

registers in word mode, only 8 bits of the data are stored from the registers; the upper bits are sign-

extended.

If the DSP registers are used as destination registers in word mode, the load is to the upper word of

the register, with the exception of A0G, A1G. When data is loaded to any register other than A0G,

A1G, the lower word of the register is cleared to 0. In the case of the A0, A1 registers, the data

sign is extended and stored in the guard bits; the lower word is cleared to 0. When the A0G, A1G

registers are the destination registers in word mode, the least significant 8 bits of the data are

loaded into the registers; the A0, A1 registers are not zero cleared but retain their previous values.

If the DSP registers are used as source registers in longword mode, when data is stored from any

registers other than A0G, A1G, the 32 bits (data) of the register are transferred. When the A0, A1

registers are used as the source registers the guard bits are disregarded. When the A0G, A1G

registers are the source registers in longword mode, only 8 bits of the data are stored from the

registers; the upper bits are sign-extended.

If the DSP registers are used as destination registers in longword mode, the load is to the 32 bits of

the register, with the exception of A0G, A1G. In the case of the A0, A1 registers, the data sign is

extended and stored in the guard bits. When the A0G, A1G registers are the destination registers in

longword mode, the least significant 8 bits of the data are loaded into the registers; the A0, A1

registers are not zero cleared but retain their previous values.

Tables 2.4 and 2.5 indicate the register data formats for DSP instructions. Some registers cannot

be accessed by certain instructions. For example, the PMULS instruction can designate the A1

for details.

Figure 2.8 shows the relationship between the buses and the DSP registers during transfers.

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