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SH7616 Datasheet(PDF) 102 Page - Renesas Technology Corp

Part # SH7616
Description  32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7600 Series
PDF  935 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7616 Datasheet(HTML) 102 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Mar 09, 2006 page 76 of 906
REJ09B0292-0200
The instruction codes, operation, and execution states of the CPU instructions are listed by
classification with the formats listed in below.
Instruction
Instruction Code
Operation
Execution
Cycles
T Bit
Indicated by mnemonic
Explanation of Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
2
Indicated in MSB
↔
LSB order
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
iiii: Immediate data
dddd: Displacement
Indicates summary of
operation
Explanation of Symbols
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in the SR
&: Logical AND of each bit
|: Logical OR of each bit
^: Exclusive OR of each bit
~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Value when
no wait
states are
inserted*
1
Value of T bit
after
instruction is
executed
Explanation of
Symbols
—: No change
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums.
The actual number of cycles may be increased when (1) contention occurs between
instruction fetches and data access, or (2) when the destination register of the load
instruction (memory
→ register) and the register used by the next instruction are the
same.
2. Depending on the instruction’s operand size, scaling is
×1, ×2, or ×4. For details, see
the SH-1/SH-2/SH-DSP Software Manual.



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