SH7727 datasheet(126/1109 Pages) RENESAS

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SH7727 Datasheet(PDF) 126 Page - Renesas Technology Corp

Part #	SH7727

Description	Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

PDF	1109 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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126 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 54 of 1034

REJ09B0254-0500

/* The value to be added to the address register depends on addressing

operations.

For example, (+2 or R8[Ix] or +0) means that

+2 : if operation is increment

R8[Ix] : if operation is add-index-reg

+0 : if operation is not-update

function modulo ( AddrReg, Index ) {

if ( AdrReg[15:0]==ME ) AdrReg[15:0]==MS;

else AdrReg=AdrReg+Index;

return AddrReg;

}

2.4.3

CPU Instruction Formats

Table 2.14 shows the instruction formats, and the meaning of the source and destination operands,

for instructions executed by the CPU core. The meaning of the operands depends on the

instruction code. The following symbols are used in the table.

xxxx:

Instruction code

mmmm: Source register

nnnn:

Destination register

iiii:

Immediate data

dddd:

Displacement

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