SH7727 datasheet(137/1109 Pages) RENESAS

137 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 65 of 1034

REJ09B0254-0500

Table 2.19 CPU Instruction Types

Type

Kinds of

Instruction Op Code

Function

Number of

Instructions

Data transfer

instructions

MOV

Data transfer

Immediate data transfer

Peripheral module data transfer

Structure data transfer

MOVA

Effective address transfer

MOVT

T bit transfer

SWAP

Upper/lower swap

XTRCT

Extraction of middle of linked registers

ADD

Binary addition

ADDC

Binary addition with carry

Arithmetic

operation

instructions

ADDV

Binary addition with overflow check

CMP/cond

Comparison

DIV1

Division

DIV0S

Signed division initialization

DIV0U

Unsigned division initialization

DMULS

Signed double-precision multiplication

DMULU

Unsigned double-precision multiplication

Decrement and test

EXTS

Sign extension

EXTU

Zero extension

MAC

Multiply-and-accumulate, double-

precision multiply-and-accumulate

MUL

Double-precision multiplication

(32

× 32 bits)

MULS

Signed multiplication (16

× 16 bits)

MULU

Unsigned multiplication (16

× 16 bits)

NEG

Sign inversion

NEGC

Sign inversion with borrow

SUB

Binary subtraction

SUBC

Binary subtraction with carry

SUBV

Binary subtraction with underflow

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