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SH7727 Datasheet(PDF) 138 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 138 Page - Renesas Technology Corp |
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138 / 1109 page ![]() Section 2 CPU Rev. 5.00 Dec 12, 2005 page 66 of 1034 REJ09B0254-0500 Type Kinds of Instruction Op Code Function Number of Instructions 6 AND Logical AND 14 NOT Bit inversion Logic operation instructions OR Logical OR TAS Memory test and bit setting TST Logical AND and T bit setting XOR Exclusive logical OR 12 ROTL 1-bit left shift 16 Shift instructions ROTR 1-bit right shift ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift SHLR Logical 1-bit right shift SHLRn Logical n-bit right shift SHAD Arithmetic dynamic shift SHLD Logical dynamic shift Branch instructions 9 BF Conditional branch, delayed conditional branch (T = 0) 11 BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure |
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