HD6433713 datasheet(134/324 Pages) RENESAS

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7.5.3 Pin Functions

Table 7-15 shows the port 5 pin functions.

Table 7-15 Port 5 Pin Functions

Pin Functions and Selection Method

P57/FS8 to

After designation of the segment pins to be used in bits SR4 to SR0 of the VFD

P50/FS15

segment control register (VFSR), bit VFDE in the digit beginning register (DBR)

is set to 1 and VFD controller/driver operation is started. During key scan

intervals, pins designated for segment output can be used by the CPU as

general-purpose ports. Even while the VFD controller/driver is operating, it is

possible to switch segment pins to general-purpose ports by writing 0 in the

VFLAG bit of VFSR.

VFLAG

Pin function

Pins P57 to P50 are all

Pins designated by bits

general-purpose I/O pins.

SR4 to SR0 are segment

output pins.* Other pins

are for general I/O.

Note: * When a pin functioning as a segment output pin is read, the value of

the corresponding bit in PDR5 is read.

7.5.4 Pin States

Table 7-16 shows the port 5 pin states in each operating mode.

Table 7-16 Port 5 Pin States

Pins

Reset

Sleep

Standby

Watch

Subactive

Active

P57/FS8 to

High

Normal

P50/FS15

impedance or state

impedance or impedance or impedance or operation

pulled down

retained

pulled down

123

HD6433713 Datasheet(PDF) 134 Page - Renesas Technology Corp

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