7702 datasheet(34/217 Pages) RENESAS

34 / 217 page

CENTRAL PROCESSING UNIT (CPU)

2.1 Central processing unit

2–8

7702/7703 Group User’s Manual

2.1.9 Processor status register (PS)

The processor status register is an 11-bit register.

Figure 2.1.5 shows the structure of the processor status register.

Note: “0” is always read from each of bits 15–11.

b15

b14

b10

b11

b12

b13

IPL

Processor staus

Fig. 2.1.5 Processor status register structure

(1)

Bit 0: Carry flag (C)

It retains a carry or a borrow generated in the arithmetic and logic unit (ALU) during an arithmetic

operation. This flag is also affected by shift and rotate instructions. When the BCC or BCS instruction

is executed, this flag’s contents determine whether the program causes a branch or not.

Use the SEC or SEP instruction to set this flag to “1,” and use the CLC or CLP instruction to clear

it to “0.”

(2)

Bit 1: Zero flag (Z)

It is set to “1” when a result of an arithmetic operation or data transfer is “0,” and cleared to “0” when

otherwise. When the BNE or BEQ instruction is executed, this flag’s contents determine whether the

program causes a branch or not.

Use the SEP instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.”

Note: This flag is invalid in the decimal mode addition (the ADC instruction).

(3)

Bit 2: Interrupt disable flag (I)

It disables all maskable interrupts (interrupts other than watchdog timer, the BRK instruction, and

zero division). Interrupts are disabled when this flag is “1.” When an interrupt request is accepted,

this flag is automatically set to “1” to avoid multiple interrupts. Use the SEI or SEP instruction to set

this flag to “1,” and use the CLI or CLP instruction to clear it to “0.” This flag is set to “1” at reset.

(4)

Bit 3: Decimal mode flag (D)

It determines whether addition and subtraction are performed in binary or decimal. Binary arithmetic

is performed when this flag is “0.” When it is “1,” decimal arithmetic is performed with each word

treated as two or four digits decimal (determined by the data length flag). Decimal adjust is automatically

performed. Decimal operation is possible only with the ADC and SBC instructions. Use the SEP

instruction to set this flag to “1,” and use the CLP instruction to clear it to “0.” This flag is cleared

to “0” at reset.

(5)

Bit 4: Index register length flag (x)

It determines whether each of index register X and index register Y is used as a 16-bit register or

an 8-bit register. That register is used as a 16-bit register when this flag is “0,” and as an 8-bit

to clear it to “0.” This flag is cleared to “0” at reset.

Note: When transferring data between registers which are different in bit length, the data is transferred

with the length of the destination register, but except for the TXA, TYA, TXB, TYB and TXS

instructions. Refer to “7700 Family Software Manual” for details.

7702 Datasheet(PDF) 34 Page - Renesas Technology Corp

7702 Datasheet(HTML) 34 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL