7702 datasheet(52/217 Pages) RENESAS

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7702/7703 Group User’s Manual

CENTRAL PROCESSING UNIT (CPU)

2–26

Processor mode

CNVss pin level

Processor mode bits

Single-chip mode

Vss (0 V) (Note 1)

Memory expansion mode

Vss (0 V) (Note 1)

Microprocessor mode

Vss (0 V) (Note 1)

Vcc (5 V) (Note 2)

2.5 Processor modes

Notes 1: The microcomputer starts operating in the single-chip mode after a reset. The microcomputer can

be switched to the other processor modes by setting the processor mode bits.

2: The microcomputer starts operating in the microprocessor mode after a reset. The microcomputer

cannot operate in the other modes, so that fix the processor mode bits as follows:

•b1 = “1” and b0 = “0.”

Table 2.5.2 Methods for setting processor modes

Bit

Bit name

Functions

At reset

Processor mode bits

Software reset bit

Interrupt priority detection time

select bits

Clock

output select bit

(Note 2)

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Microprocessor mode

1 1 : Not selected

The microcomputer is reset by

writing “1” to this bit. The value is

“0” at reading.

0 0 : 7 cycles of

0 1 : 4 cycles of

1 0 : 2 cycles of

1 1 : Not selected

0 : Clock

output disabled

(P42 functions as a programmable

I/O port.)

1 : Clock

output enabled

(P42 functions as a clock

out-

put pin.)

b1 b0

b5 b4

Processor mode register (Address 5E16)

(Note1)

Notes 1: While supplying the Vcc level to the CNVss pin, this bit becomes “1”

after a reset. (Fixed to “1.”)

2: This bit is ignored in the microprocessor mode. (It may be either “0” or “1.”)

Wait bit

Fix this bit to “0.”

0 : Software Wait is inserted when

accessing external area.

1 : No software wait is inserted

when accessing external area.

: Bits 7 to 2 are not used for setting of the processor mode.

Fig. 2.5.4 Structure of processor mode register

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