7702 datasheet(77/217 Pages) RENESAS

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7702/7703 Group User’s Manual

INTERRUPTS

4–15

4.7 Sequence from acceptance of interrupt request to execution of interrupt routine

Fig. 4.7.2 INTACK sequence timing (at minimum)

Fig. 4.7.1 Sequence from acceptance of interrupt request to execution of interrupt routine

@ : Duration for detecting interrupt priority

level

Interrupt request occurs.

Interrupt request is accepted.

Instruction

INTACK sequence

Instructions in interrupt routine

Interrupt response time

Time

Time from the occurrence of an interrupt request until the completion of executing an instruction

which is being executed at the occurrence.

Time from the instruction next to (Note) until the completion of executing an instruction which is

being done at the end of priority detection

Note : At this time, interrupt priority detection starts.

Time required to execute the INTACK sequence (13 cycles of

at minimum)

qWhen stack pointer (S)’s contents is even and no Wait

PCH

([S]–1)H

FF16

ADH

PCH

PSH

FF16

Interrupt

disable

flag (I)

Internal

clock

CPU

PCL

PSL

XX16

ADH

ADL

PCL

XX16

ADL

[S]H

[S]L

INTACK sequence

Op-code

: Not used

[S]

XX16

ADH

ADL

: Contents of stack pointer (S)

: Low-order 8 bits of vector address

: Contents of vector address (High-order address)

: Contents of vector address (Low-order address)

CPU

([S]–2)H ([S]–3)H ([S]–4)H ([S]–5)H ([S]–5)H

([S]–1)L ([S]–2)L ([S]–3)L ([S]–4)L ([S]–5)L ([S]–5)L

: CPU standard clock

: High-order 8 bits of CPU internal address bus

: Middle-order 8 bits of CPU internal address bus

: Low-order 8 bits of CPU internal address bus

: CPU internal data bus for odd address

: CPU internal data bus for even address

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