7702 datasheet(75/217 Pages) RENESAS

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7702/7703 Group User’s Manual

INTERRUPTS

4–13

4.6 Interrupt priority level detection time

After sampling had started, an interrupt priority level detection time has elapses before an interrupt request

is accepted. The interrupt priority level detection time can be selected by software. Figure 4.6.1 shows the

interrupt priority level detection time.

As the interrupt priority level detection time, normally select “2 cycles of internal clock

φ.”

4.6 Interrupt priority level detection time

Fig. 4.6.1 Interrupt priority level detection time

(2) Interrupt priority level detection time

Op code fetch cycle

Sampling pulse

(a) 7 cycles

(b) 4 cycles

Interrupt priority level

detection time

(Note)

Note: Pulse exists when “2 cycles of

” is selected.

0 0

0 1

1 0

1 1

Processor mode register (Address 5E16)

Processor mode bits

Software reset bit

Fix to “0.”

Clock

output select bit

7 cycles of

[(a) shown below]

4 cycles of

[(b) shown below]

2 cycles of

[(c) shown below]

Interrupt priority detection time select bits

Do not select

(1) Interrupt priority detection time select bits

b5, b4

Wait bit

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