7702 datasheet(39/217 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7702/7703 Group User’s Manual

2–13

2.2 Bus interface unit

The CPU and the bus send or receive data via BIU because each operates based on different clocks

(Note). The BIU allows the CPU to operate at high speed without waiting for access to the memory•I/O

devices that require a long access time.

The BIU’s functions are described bellow.

Note: The CPU operates based on

φCPU. The period of φCPU is normally the same as that of the internal

clock

φ. The internal bus operates based on the E signal. The period of the E signal is twice that

of the internal clock

φ at a minimum.

(1)

Reading out instruction (Instruction prefetch)

When the CPU does not require to read or write data, that is, when the bus is not in use, the BIU

reads instructions from the memory and stores them in the instruction queue buffer. This is called

instruction prefetch.

The CPU reads instructions from the instruction queue buffer and executes them, so that the CPU

can operate at high speed without waiting for access to the memory which requires a long access

time.

When the instruction queue buffer becomes empty or contains only 1 byte of an instruction, the BIU

performs instruction prefetch. The instruction queue buffer can store instructions up to 3 bytes.

The contents of the instruction queue buffer is initialized when a branch or jump instruction is

executed, and the BIU reads a new instruction from the destination address.

When instructions in the instruction queue buffer are insufficient for the CPU’s needs, the BIU

extends the pulse duration of clock

φCPU in order to keep the CPU waiting until the BIU fetches the

required number of instructions or more.

(2)

Reading data from memory•I/O device

The CPU specifies the storage address of data to be read to the BIU’s data address register, and

requires data. The CPU waits until data is ready in the BIU.

The BIU outputs the address received from the CPU onto the address bus, reads contents at the

specified address, and takes it into the data buffer.

The CPU continues processing, using data in the data buffer.

However, if the BIU uses the bus for instruction prefetch when the CPU requires to read data, the

BIU keeps the CPU waiting.

(3)

Writing data to memory•I/O device

The CPU specifies the address of data to be written to the BIU’s data address register. Then, the

CPU writes data into the data buffer. The BIU outputs the address received from the CPU onto the

address bus and writes data in the data buffer into the specified address.

The CPU advances to the next processing without waiting for completion of BIU’s write operation.

However, if the BIU uses the bus for instruction prefetch when the CPU requires to write data, the

BIU keeps the CPU waiting.

(4)

Bus control

To perform the above operations (1) to (3), the BIU inputs and outputs the control signals, and

controls the address bus and the data bus. The cycle in which the BIU controls the bus and accesses

the memory•I/O device is called the bus cycle.

Refer to “Chapter 12. CONNECTION WITH EXTERNAL DEVICES” about the bus cycle at accessing

the external devices.

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