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7702 Datasheet(PDF) 95 Page - Renesas Technology Corp |
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7702 Datasheet(HTML) 95 Page - Renesas Technology Corp |
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95 / 217 page ![]() TIMER A 7702/7703 Group User’s Manual 5–7 5.2 Block description 5.2.4 Timer Ai interrupt control register Figure 5.2.4 shows the structure of the timer Ai interrupt control register. For details about interrupts, refer to “Chapter 4. INTERRUPTS.” Fig. 5.2.4 Structure of timer Ai interrupt control register (1) Interrupt priority level select bits (bits 2 to 0) These bits select a timer Ai interrupt’s priority level. When using timer Ai interrupts, select priority levels 1 to 7. When a timer Ai interrupt request occurs, its priority level is compared with the processor interrupt priority level (IPL), so that the requested interrupt is enabled only when its priority level is higher than the IPL. (However, this applies when the interrupt disable flag (I) = “0.”) To disable timer Ai interrupts, set these bits to “0002” (level 0). (2) Interrupt request bit (bit 3) This bit is set to “1” when the timer Ai interrupt request occurs. This bit is automatically cleared to “0” when the timer Ai interrupt request is accepted. This bit can be set to “1” or “0” by software. b7 b6 b5 b4 b3 b2 b1 b0 Bit 7 to 4 Interrupt request bit 2 1 0 Bit name At reset 0 RW Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Interrupt priority level select bits 3 RW RW RW RW – Undefined 0 0 0 Nothing is assigned. Note: Use the SEB or CLB instruction to set each interrupt control register. Timer Ai interrupt control registers (i = 0 to 4) (Addresses 7516 to 7916) |
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