7702 datasheet(31/217 Pages) RENESAS

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7702/7703 Group User’s Manual

2.1 Central processing unit

CENTRAL PROCESSING UNIT (CPU)

2–5

2.1.5 Program counter (PC)

The program counter is a 16-bit counter that indicates the low-order 16 bits of the address (24 bits) at

which an instruction to be executed next (in other words, an instruction to be read out from an instruction

queue buffer next) is stored. The contents of the high-order program counter (PCH) become “FF16,” and the

low-order program counter (PCL) becomes “FE16” at reset. The contents of the program counter becomes

the contents of the reset’s vector address (addresses FFFE16, FFFF16) immediately after reset.

Figure 2.1.3 shows the program counter and the program bank register.

Fig. 2.1.3 Program counter and program bank register

2.1.6 Program bank register (PG)

The program bank register is an 8-bit register. This register indicates the high-order 8 bits of the address

(24 bits) at which an instruction to be executed next (in other words, an instruction to be read out from an

instruction queue buffer next) is stored. These 8 bits are called bank.

When a carry occurs after adding the contents of the program counter or adding the offset value to the

contents of the program counter in the branch instruction and others, the contents of the program bank

program counter, the contents of the program bank register is automatically decremented by 1. Accordingly,

there is no need to consider bank boundaries in programming, usually.

In the single-chip mode, make sure to prevent the program bank register from being set to the value other

than “0016” by executing the branch instructions and others. It is because the access space of the single-

chip mode is the internal area within the bank 016.

This register is cleared to “0016” at reset.

PCH

PCL

b0 b15

b8 b7

(b16)

(b23)

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