7702 datasheet(72/217 Pages) RENESAS

72 / 217 page

7702/7703 Group User’s Manual

INTERRUPTS

4–10

4.4 Interrupt priority level

When two or more interrupt requests are detected at the same sampling timing, at which whether an

interrupt request exists or not is checked, in the case of the interrupt disable flag (I) = “0” (interrupts

enabled); they are accepted in order of priority levels, with the highest priority interrupt request accepted

first.

Among a total of 19 interrupt sources, the user can set the desired priority levels for 16 interrupt sources

except software interrupts (zero division and BRK instruction interrupts) and the watchdog timer interrupt.

Use the interrupt priority level select bits to set their priority levels. Additionally, the reset, which is handled

as one that has the highest priority of all interrupts, and the watchdog timer interrupt have their priority levels

set by hardware. Figure 4.4.1 shows the interrupt priority levels set by hardware.

Note that software interrupts are not affected by interrupt priority levels. Whenever the instruction is executed,

a branch is certain to be made to the interrupt routine.

Fig. 4.4.1 Interrupt priority levels set by hardware

4.4 Interrupt priority level

Watchdog

timer

Reset

16 interrupt sources except software interrupts

and watchdog timer interrupt

The user can set the desired priority levels inside of the dotted line.

Priority levels determined by hardware

High

Low

Priority level

••••••••••••••••••

7702 Datasheet(PDF) 72 Page - Renesas Technology Corp