7702 datasheet(91/217 Pages) RENESAS

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TIMER A

7702/7703 Group User’s Manual

5–3

5.2 Block description

Figure 5.2.1 shows the block diagram of Timer A. Explanation of relevant registers to Timer A is described

below.

However, for the following registers, refer to the relevant section:

•Up-down register (address 4416) ....................... “5.4.2 Operation in event counter mode”

•One-shot start register (address 4216) ............. “5.5.3 Trigger”

Fig. 5.2.1 Block diagram of Timer A

Data bus (odd)

Data bus (even)

f 2

f 16

f 64

f 512

Count source

Timer mode

One- shot pulse mode

PWM mode

Polarity

switching

Timer mode

(Gate function)

Event counter mode

Trigger

Count start bit

Down-count

Up-down bit

( Low-order 8 bits )

(High-order 8 bits)

Timer Ai reload register (16)

Timer Ai counter(16)

Timer Ai

interrupt

request bit

Up-count/down-count

switching

(Always down-count except

for event counter mode)

Toggle

F.F.

Pulse output

function select bit

TAi IN

TAi OUT

select bits

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