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7702 Datasheet(PDF) 60 Page - Renesas Technology Corp |
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7702 Datasheet(HTML) 60 Page - Renesas Technology Corp |
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60 / 217 page ![]() INPUT/OUTPUT PINS 3–6 7702/7703 Group User’s Manual Figures 3.1.4 and 3.1.5 show the port peripheral circuits. 3.1 Programmable I/O ports Fig. 3.1.4 Port peripheral circuits (1) Ports P00/A0 to P07/A7, P10/A8/D8 to P17/A15/D15, P20/A16/D0 to P27/A23/D7, P30/R/W to P33/HLDA, P43 to P46 [Inside dotted-line not included] Data bus Direction register Port latch Ports P42/ 1, P83/TxD0, P87/TxD1 [Inside dotted-line not included. ] Ports P50/TA0OUT, P52/TA1OUT, P54/TA2OUT, P56/TA3OUT, P60/TA4OUT [Inside dotted-line included. ] Data bus “1” Output Port latch Direction register P82/RxD0, P86/RxD1 Ports P40/HOLD, P41/RDY, P47, P51/TA0 IN, P53/TA1IN, P55/TA2 IN, P57/TA3 IN, [Inside dotted-line included] P61/TA4IN, P62/INT0 to P64/INT2, P65/TB0IN to P67/TB2IN, (There is no hysteresis for P82/RxD0 and P86/RxD1.) Ports P70/AN0 to P76/AN6 Port P77/AN7/ADTRG Data bus Analog input Direction register Port latch [Inside dotted-line not included. ] [Inside dotted-line included. ] 7703 Group There are not pins P33, P43 – P46, P60, P61, P66, P67, P73 – P76. |
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