7702 datasheet(82/217 Pages) RENESAS

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7702/7703 Group User’s Manual

INTERRUPTS

4–20

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4.10 External interrupts (INTi interrupt)

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An external interrupt request occurs by input signals to the INTi (i = 0 to 2) pin. The occurrence factor of

interrupt request can be selected by the level sense/edge sense select bit and the polarity select bit (bits

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5 and 4 at addresses 7D16 to 7F16) shown in Figure 4.10.1. Table 4.10.1 lists the occurrence factor of INTi

interrupt request.

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When using P62/INT0 to P64/INT2 pins as input pins of external interrupts, set the corresponding bits at

address 1016 (port P6 direction register) to “0.” (Refer to Figure 4.10.2.)

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The signals input to the INTi pin require “H” or “L” level width of 250 ns or more independent of the f(XIN).

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Additionally, even when using the pins P62/INT0 to P64/INT2 as the input pins of external interrupt, the user

can obtain the pin’s state by reading bits 2 to 4 at address E16 (port P6 register).

Note: When selecting an input signal’s falling or “L” level as the occurrence factor of an interrupt request,

make sure that the input signal is held “L” for 250 ns or more. When selecting an input signal’s rising

or “H” level as that, make sure that the input signal is held “H” for 250 ns or more.

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4.10 External interrupts (INTi interrupt)

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Table 4.10.1 Occurrence factor of INTi interrupt request

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INTi interrupt request occurrence factor

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The INTi interrupt request occurs by always detecting the INTi pin’s state. Accordingly, when the user does

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not use the INTi interrupt, set the INTi interrupt’s priority level to level 0.

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Interrupt request occurs at falling of the signal input to the INTi pin (edge sense).

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Interrupt request occurs at rising of the signal input to the INTi pin (edge sense).

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Interrupt request occurs while the INTi pin level is “H” (level sense).

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Interrupt request occurs while the INTi pin level is “L” (level sense).

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