7702 datasheet(68/217 Pages) RENESAS

68 / 217 page

7702/7703 Group User’s Manual

INTERRUPTS

4–6

4.3 Interrupt control

The enabling and disabling of maskable interrupts are controlled by the following :

•Interrupt request bit

•Interrupt priority level select bits

•Processor interrupt priority level (IPL)

•Interrupt disable flag (I)

The interrupt disable flag (I) and the processor interrupt priority level (IPL) are assigned to the processor

status register (PS). The interrupt request bit and the interrupt priority level select bits are assigned to the

interrupt control register of each interrupt.

Figure 4.3.1 shows the memory assignment of the interrupt control registers, and Figure 4.3.2 shows their

structure.

qMaskable interrupt: An interrupt of which request’s acceptance can be disabled by software.

qNon-maskable interrupt (including Zero division, BRK instruction, Watchdog timer interrupts):

An interrupt which is certain to be accepted when its request occurs. These interrupts do not have their

interrupt control registers and are independent of the interrupt disable flag (I).

4.3 Interrupt control

Fig. 4.3.1 Memory assignment of interrupt control registers

A-D conversion interrupt control register

UART0 transmit interrupt control register

UART0 receive interrupt control register

UART1 transmit interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

INT0 interrupt control register

INT1 interrupt control register

INT2 interrupt control register

Address

7016

7116

7216

7316

7416

7516

7616

7716

7816

7916

7A16

7B16

7C16

7D16

7E16

7F16

7702 Datasheet(PDF) 68 Page - Renesas Technology Corp

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