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7702 Datasheet(PDF) 69 Page - Renesas Technology Corp |
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7702 Datasheet(HTML) 69 Page - Renesas Technology Corp |
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69 / 217 page  7702/7703 Group User’s Manual 4–7 INTERRUPTS 4.3 Interrupt control Fig. 4.3.2 Structure of interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16) Bit 4 Interrupt request bit (Note 1) 2 1 0 Bit name At reset 0 RW Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request 0 : Edge sense 1 : Level sense Notes 1: The INT0 to INT2 interrupt request bits are invalid when selecting the level sense. 2: Use the SEB or the CLB instruction to set the INT0 to INT2 interrupt control registers. Interrupt priority level select bits 3 7, 6 5 RW RW RW RW RW RW – 0 0 Undefined 0 0 0 Polarity select bit 0 : Set the interrupt request bit at “H” level for level sense and at falling edge for edge sense. 1 : Set the interrupt request bit at “L” level for level sense and at rising edge for edge sense. Level sense/Edge sense select bit Nothing is allocated. b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion, UART0 and 1 transmit, UART0 and 1 receive, timers A0 to A4, timers B0 to B2 interrupt control registers (Addresses 7016 to 7C16) Bit 7 to 4 Interrupt request bit 2 1 0 Bit name At reset 0 RW Functions 0 0 0 : Level 0 (Interrupt disabled) 0 0 1 : Level 1 Low level 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 High level b2 b1 b0 0 : No interrupt request 1 : Interrupt request Note: Use the SEB or CLB instruction to set each interrupt control register. Interrupt priority level select bits 3 RW RW RW RW – Undefined 0 0 0 Nothing is allocated. |
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