7702 datasheet(83/217 Pages) RENESAS

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7702/7703 Group User’s Manual

INTERRUPTS

4–21

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4.10 External interrupts (INTi interrupt)

INT0 to INT2 interrupt control registers (Addresses 7D16 to 7F16)

Bit

Interrupt request bit (Note 1)

Bit name

At reset

Functions

0 0 0 : Level 0 (Interrupt disabled)

0 0 1 : Level 1

Low level

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

High level

b2 b1 b0

0 : No interrupt request

1 : Interrupt request

0 : Edge sense

1 : Level sense

Notes 1: The INT0 to INT2 interrupt request bits are invalid when selecting the level sense.

2: Use the SEB or CLB instruction to set the INT0 to INT2 interrupt control registers.

Interrupt priority level select bits

7, 6

–

Undefined

Polarity select bit

0 : Set the interrupt request bit at

“H” level for level sense and at

falling edge for edge sense.

1 : Set the interrupt request bit at

“L” level for level sense and at

rising edge for edge sense.

Level sense/Edge sense select bit

Nothing is allocated.

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Fig. 4.10.1 Structure of INTi (i=0 to 2) interrupt control register

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