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7702 Datasheet(PDF) 76 Page - Renesas Technology Corp |
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7702 Datasheet(HTML) 76 Page - Renesas Technology Corp |
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76 / 217 page ![]() 7702/7703 Group User’s Manual INTERRUPTS 4–14 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described below. When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt is cleared to “0,” and then the interrupt processing starts from the next cycle of completion of the instruction which is being executed at accepting the interrupt request. Figure 4.7.1 shows the sequence from acceptance of interrupt request to execution of interrupt routine. After execution of an instruction at accepting the interrupt request is completed, an INTACK (Interrupt Acknowledge) sequence is executed, and a branch is made to the start address of the interrupt routine allocated in addresses 016 to FFFF16. The INTACK sequence is automatically performed in the following order. The contents of the program bank register (PG) just before performing the INTACK sequence are stored to stack. The contents of the program counter (PC) just before performing the INTACK sequence are stored to stack. The contents of the processor status register (PS) just before performing the INTACK sequence is stored to stack. The interrupt disable flag (I) is set to “1.” The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level (IPL). The contents of the program bank register (PG) are cleared to “0016,” and the contents of the interrupt vector address are set into the program counter (PC). Performing the INTACK sequence requires at least 13 cycles of internal clock φ. Figure 4.7.2 shows the INTACK sequence timing. Execution is started beginning with an instruction at the start address of the interrupt routine after completing the INTACK sequence. 4.7 Sequence from acceptance of interrupt request to execution of interrupt routine |
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