7702 datasheet(80/217 Pages) RENESAS

80 / 217 page

7702/7703 Group User’s Manual

INTERRUPTS

4–18

4.8 Return from interrupt routine

When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank

INTACK sequence, which were saved to the stack area, are automatically restored, and control returns to

the routine executed before the acceptance of interrupt request and processing is resumed from it left off.

For any register that is saved by software in the interrupt routine, restore it with the same data length and

same register length as it was saved by using the PUL instruction and others before executing the RTI

instruction.

4.9 Multiple interrupts

When a branch is made to the interrupt routine, the microcomputer becomes the following situation:

•Interrupt disable flag (I) = “1” (interrupts disabled)

•Interrupt request bit of the accepted interrupt = “0”

•Processor interrupt priority level (IPL) = interrupt priority level of the accepted interrupt

Accordingly, as long as the IPL remains unchanged, the microcomputer can accept the interrupt request that

has higher priority than the interrupt request being executed now by clearing the interrupt disable flag (I)

to “0” in the interrupt routine. This is multiple interrupts.

Figure 4.9.1 shows the multiple interrupt mechanism.

The interrupt requests that have not been accepted owing to their low priority levels are retained. When the

RTI instruction is executed, the interrupt priority level of the routine that the microcomputer was executing

before accepting the interrupt request is restored to the IPL. Therefore, one of the interrupt requests being

retained is accepted when the following condition is satisfied at next detection of interrupt priority level:

Interrupt priority level of interrupt request being retained > Restored processor interrupt priority level (IPL)

4.8 Return from interrupt routine 4.9 Multiple interrupts

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