HC210 datasheet(194/228 Pages) ALTERA

194 / 228 page

8–6

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

HardCopy II devices offer three distinct types of I/O elements (IOEs)

which support a variety of I/O features to match Stratix II IOEs. These are

memory interface IOEs, high-speed IOEs, and general purpose IOEs.

Memory interface IOEs support popular I/O standards used by external

memory devices, including single-ended standards from LVTTL,

LVCMOS to SSTL, and HSTL voltage referenced (VREF) type I/O

standards. Memory interface IOEs also have PCI clamp circuitry for PCI

support.

High-speed IOEs support differential applications utilizing LVDS and

HyperTransport technology. High-speed IOEs also support single-ended

LVTTL and LVCMOS I/O standards, but do not support VREF I/O

standards.

General purpose IOEs support LVTTL and LVCMOS I/O standards.

General purpose IOEs on the bottom I/O banks (banks 7 and 8) also have

PCI clamping circuitry to support the PCI interface on HardCopy II

devices.

Table 8–4. Package Options and I/O Pin Counts for Stratix II and HardCopy II Companion Devices Notes (1),

(2)

Stratix II

Device

HC210

HC220

HC230 (3)

HC240 (4)

484-Pin

FineLine BGA

672-Pin

FineLine BGA

780-Pin

FineLine BGA

1,020-Pin

FineLine BGA

1,020-Pin

FineLine BGA

1,508-Pin

FineLine BGA

EP2S30

334

EP2S60

334

492

EP2S90

308

494

698

EP2S130

494

698

EP2S180

698

742

951

Notes to Table 8–4:

(1)

User I/O pin counts are preliminary. The Quartus II software I/O pin counts include one additional pin,

PLL_ENA,

which is not included in this pin count. The

PLL_ENA pin is not available as a general purpose I/O pin and can

only be used to enable the PLLs in this device.

(2)

All I/O pin counts include eight dedicated clock input pins (

clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,

clk11p, and clk11n) that can be used for data inputs.

(3)

The I/O pin counts for all HC230 combinations include four dedicated fast PLL clock inputs (

FPLL7CLKp/n,

FPLL8CLKp/n) that can be used for data inputs.

(4)

The I/O pin counts for HC240 combinations include eight dedicated fast PLL clock inputs (

FPLL7CLKp/n,

FPLL8CLKp/n, FPLL9CLKp/n, and FPLL10CLKp/n) that can be used for data inputs.

HC210 Datasheet(PDF) 194 Page - Altera Corporation

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