HC210 datasheet(198/228 Pages) ALTERA

198 / 228 page

8–10

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

SSTL-2 class I and II

Voltage referenced

2.5

SSTL-18 class I and II

Voltage referenced

1.8

1.8-V HSTL class I and II Voltage referenced

1.8

1.5-V HSTL class I and II Voltage referenced

1.5

PCI / PCI-X

Single-ended

3.3

(1)

Differential SSTL-2 class

I and II input

Pseudo differential (3)

3.3/2.5/

1.8/1.5

(2)

Differential SSTL-2 class

I and II output

Pseudo differential (3)

2.5

(2)

Differential SSTL-18

class I and II input

Pseudo differential (3)

3.3/2.5/

1.8/1.5

(2)

Differential SSTL-18

class I and II output

Pseudo differential (3)

1.8

(2)

1.8-V differential HSTL

class I and II input

Pseudo differential (3)

3.3/2.5/

1.8/1.5

(2)

1.8-V differential HSTL

class I and II output

Pseudo differential (3)

1.8

(2)

1.5-V differential HSTL

class I and II input

Pseudo differential (3)

3.3/2.5/

1.8/1.5

(2)

1.5-V differential HSTL

class I and II output

Pseudo differential (3)

1.5

(2)

LVDS

Differential

2.5

HyperTransport™

technology

Differential

2.5

Notes to Table 8–6:

(1)

Like Stratix II devices, the optional PCI clamp is only available on column I/O pins. General purpose IOEs on the

right row I/O pins do not support the PCI clamp.

(2)

Similar to Stratix II devices, these I/O standards are only available on input clock pins, output clock pins in I/O

banks 9, 10, 11, 12, and DQS pins in top I/O banks 3, 4 for all HardCopy II devices, and DQS pins in bottom I/O

banks 7 and 8 for HC230 and HC240 devices.

(3)

Pseudo-differential HSTL and SSTL inputs only use the positive polarity input in the speed path. The negative

input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with

the second output programmed as inverted. This is similar to a Stratix II device implementation.

Table 8–6. Hardcopy II Supported I/O Standards on User I/O Pins (Part 2 of 2)

I/O Standard

Type

VCCIO Level (V)

Memory

Interface

IOEs

General

Purpose

IOEs

High-

Speed

IOEs

Input

Output

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