HC210 datasheet(200/228 Pages) ALTERA

200 / 228 page

8–12

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Differential

SSTL-18 class I

and II output

Pseudo

differential

(6)

1.8

1.8-V differential

HSTL class I

and II input

Pseudo

differential

(6)

3.3/2.5/

1.8/1.5

1.8-V differential

HSTL class I

and II output

Pseudo

differential

(6)

1.8

1.5-V differential

HSTL class I

and II input

Pseudo

differential

(6)

3.3/2.5/

1.8/1.5

1.5-V differential

HSTL class I

and II output

Pseudo

differential

(6)

1.5

LVDS input

Differential

2.5

LVDS output

Differential

2.5

HyperTransport

technology input

Differential

2.5

HyperTransport

technology

output

Differential

2.5V

LVPECL input

Differential

3.3/2.5/

1.8/1.5

(7)

Notes to Table 8–7:

(1)

CLK8 and CLK10 pins on HC210, HC220, and HC230 devices do not support differential standards LVDS and

HyperTransport technology. Only LVTTL is supported on these

CLK pins for these devices.

(2)

CLK[4..7] pins on HC210 and HC220 devices do not support SSTL, HSTL, differential SSTL, and HSTL input or

output.

(3)

HC230 only has two fast PLL clocks,

FPLL[7..8]CLK. HC240 has four FPLL clocks, FPLL[7..10]CLK.

(4)

HC210 and HC220

PLL6_OUT pins do not support SSTL, HSTL, differential SSTL, and HSTL input or output.

(5)

HC210 and HC220

PLL6_FB pins do not support SSTL, HSTL, differential SSTL, and HSTL input or output.

(6)

Pseudo-differential HSTL and SSTL inputs only use the positive polarity input in the speed path. The negative

input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with

the second output programmed as inverted. This is similar to a Stratix II device implementation.

(7)

This is not supported.

Table 8–7. Hardcopy II Supported I/O Standards of Input Clocks, Clock Out, and PLL Feedback (Part 2 of 2)

I/O Standard

Type

VCCIO Level (V)

CLK[0..3,

8..11] (1)

CLK[4..7,

12..15]

(2)

FPLL_CLK

(3)

PLL_OUT

(4)

PLL_FB

(5)

Input

Output

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