HC210 datasheet(196/228 Pages) ALTERA

196 / 228 page

8–8

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Figure 8–1. HardCopy II HC240 I/O Banks

Notes (1), (2), (3), (4)

Notes to Figure 8–1:

(1)

Figure 8–1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical

representation only. Refer to the pin list and Quartus II software for exact locations.

(2)

Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and input

only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for input only

operations on PLL clock input pins. Refer to “Differential I/O Termination” on page 8–20 for more details.

(3)

HardCopy II devices and the Quartus II software does not support differential SSTL and differential HSTL

standards at left and right I/O banks. Side I/O banks do not have VREF pins.

(4)

Figure 8–1 shows the HC240 device. Other HardCopy II devices have fewer PLL blocks.

Bank 4

Memory Interface IOEs

Bank 7

Memory Interface IOEs

Bank 8

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

Bank 3

Memory Interface IOEs

Bank 2

High-Speed IOEs

Bank 1

High-Speed IOEs

Bank 5

High-Speed IOEs

Bank 6

High-Speed IOEs

PLL 1

PLL 2

PLL 4

PLL 3

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &

HyperTransport Technology

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &

HyperTransport Technology

CLK, PLL_FB input pins & PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,

& PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

PLL 5

PLL 11

Bank 11 Bank 9

PLL 6

PLL 12

Bank 12 Bank 10

PLL 10

PLL 9

PLL 7

PLL 8

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