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HC210 Datasheet(PDF) 214 Page - Altera Corporation |
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HC210 Datasheet(HTML) 214 Page - Altera Corporation |
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214 / 228 page ![]() 8–26 Altera Corporation September 2008 HardCopy Series Handbook, Volume 1 PLL Planning and Utilization Stratix II devices support enhanced PLLs and fast PLLs. HardCopy II devices also support enhanced PLLs and fast PLLs, but with two variations: ■ HardCopy II devices have a different number of PLLs than Stratix II devices. ■ HardCopy II devices may support fewer I/O standards for clock inputs and outputs. This is explained in the I/O standards support section later in this chapter. Table 8–18 shows which PLLs each HardCopy II and Stratix II device supports. The Stratix II reference columns are divided based on package, not density. Figures 8–3 to 8–5 show PLL number designations. The Stratix II devices support 6 or 12 PLLs depending on the package offering, and not the device density. The HardCopy II PLLs are not removed symmetrically from all four sides. In general, fast PLLs are removed from sides that do not support high speed IOEs since the primary use of the fast PLL on the sides is for high speed I/O interface functions. Mixed-port read-during-write Outputs set to unknown or old data Unknown output Power down of unused RAM blocks (2) vv Notes to Table 8–17: (1) Stratix II M4K blocks support .mif file loading. (2) Stratix II memory blocks remain powered up even when not used. Table 8–17. HardCopy II Embedded Memory Features (Part 2 of 2) Feature M4K Blocks M-RAM Blocks Table 8–18. Stratix II / HardCopy II Companion Device PLL Availability Guide (Part 1 of 2) Stratix II and HardCopy II Companion Devices Package Fast PLLs Enhanced PLLs 12 347 89 10 56 11 12 EP2S30 HC210 (1) 484-pin FineLine BGA vv v v EP2S60 HC210 (1) 484-pin FineLine BGA vv v v EP2S90 HC210 (1) 484-pin FineLine BGA vv v v EP2S60 HC220 (1) 672-pin FineLine BGA vv v v |
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