HC210 datasheet(218/228 Pages) ALTERA

218 / 228 page

8–30

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Figure 8–5. HC240 PLL Locations

Global and Local

Signals

HardCopy II devices have 16 clock pins (

CLK[15..0]) to drive either the

global or local clock networks. Four clock pins drive each side of the

device. This is similar to Stratix II devices; therefore, there are no

limitations when compiling designs for Stratix II devices and

HardCopy II companion devices.

Internal logic and enhanced and fast PLL outputs can also drive the

global and regional clock networks. Each global and regional clock

network has a clock control block, which controls the selection of the

clock source and allows you to dynamically enable or disable the clock

network to reduce power consumption.

FPLL10CLK

FPLL9CLK

CLK[8..11]

FPLL7CLK

FPLL8CLK

CLK[3..0]

Bank 4

Memory Interface IOEs

Bank 7

Memory Interface IOEs

Bank 8

Memory Interface IOEs

Bank 3

Memory Interface IOEs

Bank 2

High-Speed IOEs

Bank 1

High-Speed IOEs

Bank 5

High-Speed IOEs

Bank 6

High-Speed IOEs

PLL 1

PLL 2

PLL 4

PLL 3

PLL 10

PLL 9

PLL 7

PLL 8

PLL 5

PLL 11

Bank 11 Bank 9

PLL 6

PLL 12

Bank 12 Bank 10

CLK[7..4]

CLK[15..12]

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