HC210 datasheet(222/228 Pages) ALTERA

222 / 228 page

8–34

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

Figure 8–8 shows an example of a Stratix II DSP block that uses only 1 of

8 available 9 × 9 multiplier blocks and an accumulator block to implement

an 8 × 8 bit multiplication function with clock latency. When this DSP

block is implemented in the HardCopy II design, the Quartus II Compiler

chooses the appropriate entry from the macro library to implement the

9 × 9 multiplier and accumulator block which results in an optimized

logic utilization and placement flexibility.

Figure 8–8. HardCopy II Floorplan of 8 × 8 DSP Block

EP2S180

(1)

768

384

768

384

Note to Table 8–20:

(1)

If these Stratix II devices are selected with smaller HardCopy II companion devices, all Stratix II DSP resources may

not be available if all the Stratix II ALM blocks are used and fully utilized. Quartus II will determine available

resources for DSP and ALM implementation when compiling with HardCopy II devices.

Table 8–20. DSP Multiplier Availability for Stratix II and HardCopy II Companion Devices (Part 2 of 2)

Stratix II

Device

HC210

HC220

HC230

HC240

9 × 9 18 × 18 36 × 36 9 × 9 18 × 18 36 × 36 9 × 9 18 × 18 36 × 36 9 × 9 18 × 18 36 × 36

HC210 Datasheet(PDF) 222 Page - Altera Corporation