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HC210 Datasheet(PDF) 219 Page - Altera Corporation

Part # HC210
Description  HardCopy II Device Family
PDF  228 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

HC210 Datasheet(HTML) 219 Page - Altera Corporation

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Altera Corporation
8–31
September 2008
Preliminary
Stratix II ALM Adaptation into HardCopy II Logic
Table 8–19 lists the clock resources available in HardCopy II devices.
Stratix II ALM
Adaptation into
HardCopy II
Logic
The basic logic building block in the Stratix II architecture is the ALM.
Each ALM contains a variety of look-up table- (LUT-) based resources,
two programmable registers, two dedicated full adders, and various
routing resources to and from the ALM.
HardCopy II devices do not have ALM blocks, but use a fine-grain
architecture called HCells. HCells can implement all combinations of
Stratix II ALM and DSP logic. Each HardCopy II companion device
contains an abundance of HCells to implement a Stratix II design
utilizing all available ALMs. Therefore, there are no compatibility
constraints when compiling for HardCopy II devices.
When compiling a Stratix II design into a HardCopy II companion
device, the Quartus II software replaces ALM blocks used in Stratix II
with predefined HCell macros. Unused ALM resources are not
implemented in HardCopy II devices. This allows for optimal placement
of the HardCopy II floor plan and significant power savings.
Figure 8–6 shows an example of a Stratix II ALM block implementation
using only one of the registers. When compiling this Stratix II design for
a HardCopy II companion device, the Quartus II compiler replaces the
Table 8–19. Clock Network Resources and Features Available in HardCopy II
Devices
Resources and Features
Availability
Number of global clock networks
16
Number of regional clock networks
32
Global clock input sources
Clock input pins, PLL outputs, logic
array
Regional clock input sources
Clock input pins, PLL outputs, logic
array
Number of unique clock sources in a
quadrant
24 (16 global clocks and 8 regional
clocks)
Number of unique clock sources in the
entire device
48 (16 global clocks and 32 regional
clocks)
Power-down mode
Global and regional clock networks,
dual-regional clock region
Clocking regions for high fan-out
applications
Quadrant region, dual-regional, entire
device via global or regional clock
networks



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