HC210 datasheet(220/228 Pages) ALTERA

220 / 228 page

8–32

Altera Corporation

September 2008

HardCopy Series Handbook, Volume 1

ALM block with a predetermined HCell macro that implements a register

from its HardCopy II library of HCell macros. This macro entry has

predetermined timing.

Figure 8–6. Stratix II ALM Simple Registered Input and Output

Figure 8–7 shows a HardCopy II ALM register implementation showing

Clock, Data In, and Data Out originating from a small cluster of HCells.

Unused HCells are reserved for other logic implementation or powered

down.

Figure 8–7. HardCopy II Unused HCells

PRN

reg0

adder0

adder1

Combinational

Logic

dataf0

datae0

dataa

datab

datac

datad

datae1

dataf1

PRN

reg1

shared_arith_out

carry_out

reg_chain_out

reg_chain_in

carry_in

shared_arith_in

To General or

Local Routing

To General or

Local Routing

To General or

Local Routing

To General or

Local Routing

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