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HC210 Datasheet(PDF) 217 Page - Altera Corporation |
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HC210 Datasheet(HTML) 217 Page - Altera Corporation |
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217 / 228 page  Altera Corporation 8–29 September 2008 Preliminary PLL Planning and Utilization Figure 8–4. HC230 PLL Locations HC240 device fast PLLs 1, 2, 7, and 8 are located in the logic array, next to the left high speed IOEs of the device. HC240 device fast PLLs 3, 4, 9, and 10 are located in the logic array, next to the right high speed IOEs. HC240 device enhanced PLLs 5, 6, 11, and 12 are located in the logic array, next to the top and bottom memory interface IOEs. FPLL10CLK FPLL9CLK CLK[8..11] FPLL7CLK FPLL8CLK CLK[3..0] CLK[7..4] CLK[15..12] Bank 4 Memory Interface IOEs Bank 7 Memory Interface IOEs Bank 8 Memory Interface IOEs Bank 3 Memory Interface IOEs Bank 2 High-Speed IOEs Bank 1 High-Speed IOEs Bank 5 General-Purpose IOEs Bank 6 General-Purpose IOEs PLL 1 PLL 2 PLL 7 PLL 8 PLL 5 PLL 11 Bank 11 Bank 9 PLL 6 PLL 12 Bank 12 Bank 10 |
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