DP8344 datasheet(154/184 Pages) NSC

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60 Reference Section (Continued)

SUBA

Subtract with Accumulator

Syntax

SUBA

Rs Rd

SUBA

mlr

Affected Flags

N Z C V

Description

Subtracts the active accumulator from the source register

Rs and places the result into the destination specified The

destination may be either a register Rd or data memory via

an index register mode

mlr

Negative numbers are repre-

sented using the two’s complement format Note that regis-

ter bank selection determines which accumulator is active

Example

In the first example the value 4 is placed into the currently

active accumulator that accumulator is subtracted from the

contents of register 20 and then the result is placed into

MOVE

4 A

Place constant into accum

SUBA

R20 R21

R20 b accum

xR21

In the second example the alternate accumulator of regis-

ter bank B is selected and then subtracted from register 20

The result is placed into the data memory pointed to by the

index register IZ and then the value of IZ is incremented by

one

EXX

0 1

Select alt accumulator

SUBA

R20

IZa

R20 b accum

xdata mem

and increment data pointer

Instruction Format

SUBA Rs Rd

111010

Opcode

SUBA Rs

mlr

TLF9336 – 16

T-states

SUBA Rs Rd

SUBA Rs

mlr

Bus Timing

SUBA Rs Rd

Figure 6-1

SUBA Rs

mlr

Figure 6-7

Operation

SUBA Rs Rd

Rs b accumulator

xRd

SUBA Rs

mlr

Rs b accumulator

xdata memory

TRAP

Software Interrupt

Syntax

TRAP v

Affected Flags

None

Description

Pushes the Program Counter the Global Interrupt Enable bit

GIE

the ALU flags and the current register bank selec-

tions onto the internal Address Stack then unconditionally

transfers control to the instruction at the memory address

created by concatenating the contents of the Interrupt Base

bits If the value of g is equal to ‘‘1’’ then the Global Inter-

rupt Enable bit GIE will be cleared If the g operand is

omitted then g e 0 is assumed The vector number v

points to one of 64 Interrupt Table entries (range 0 to 63)

Since some of the Interrupt Table entries are used by the

hardware interrupts the TRAP instruction can simulate

hardware interrupts The following table lists the hardware

interrupts and their associated vector numbers

Hardware Interrupt Vector Table

Interrupt

(Binary)

NMI

(011100)

RFFDARA

(000100)

TFE

(001000)

LTA

(001100)

BIRQ

(010000)

(010100)

Example

Simulate the Transmitter FIFO Empty interrupt

TRAP

8 1

TFE interrupt simulation

Instruction Format

110011111

Opcode

T-states

Bus Timing

Figure 6-1

Operation

GIE

ALU flags

xAddress Stack

if g e 1

then clear GIE

Create PC address by concatonating the IBR register to

the vector number v as shown below

TLF9336 – 17

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