AD9545 datasheet(141/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 141 of 157

The previous procedure is an example of an upload sequence

consisting of two subsequences. Most upload sequences require

more than two subsequences; however, the procedure is the

same. Specifically, partition a long sequence into several

subsequences by using the pause instruction at the end of each

subsequence and the end of data instruction at the end of the

final subsequence.

EEPROM Checksum

When the EEPROM controller encounters an end of data

instruction (see Table 62) during an upload sequence, it

computes a 32-bit cyclic redundancy check (CRC) checksum

and appends it to the stored data in the EEPROM. Similarly,

when the EEPROM controller executes a download sequence, it

computes a checksum on the fly. At the end of a download

sequence, the EEPROM controller compares the newly

computed checksum to the one stored in the EEPROM. If the

two checksums do not match, the EEPROM controller asserts

the EEPROM CRC error bit in the status readback section of

the register map.

To minimize the possibility of downloading a corrupted

EEPROM data set, the user can execute a checksum test by

asserting the verify EEPROM CRC bit in the EEPROM section

of the register map, which causes the EEPROM controller to

execute a download sequence, but without actually transferring

data to the AD9545 registers. The controller still computes an

on the fly checksum, performs the checksum comparison, and

asserts the EEPROM CRC error bit if the checksums do not

match. Therefore, after the device deasserts the EEPROM load

in progress bit, the user can check the EEPROM CRC fault bit

to determine if the test passed (that is, EEPROM CRC error = 0).

However, even if the test fails, device operation is unaffected

because there was no transfer of data to the AD9545 registers.

EEPROM Header

The EEPROM controller adds a header to stored data that

carries information related to the AD9545, such as

•

Vendor ID

•

Chip type

•

Product ID

•

Chip revision

At the beginning of an EEPROM download sequence, the

EEPROM controller compares the stored header values to the

values in the corresponding registers of the AD9545. If the

controller detects a mismatch, it asserts the EEPROM fault bit

in the status readback section of the register map and

terminates the download.

EEPROM INSTRUCTION SET

The EEPROM controller relies on a combination of instructions

and data. An instruction consists of a single byte (eight bits).

Some instructions require subsequent bytes of payload data.

That is, some instructions are self contained operations,

whereas others are directions on how to process subsequent

payload data. A summary of the EEPROM controller

instructions appears in Table 62.

When the controller downloads the EEPROM contents to the

AD9545 registers, it does so in a linear fashion, stepping

through the instructions stored in the EEPROM. However, when

the controller uploads to the EEPROM, the sequence is a nonlinear

combination of various parts of the register map, as well as

computed data that the controller calculates on the fly.

Instructions with a hexadecimal value from 0x00 through 0x7F

prescribe a register transfer operation. Register transfer instructions

require a 2-byte suffix, which constitutes the starting address of

the AD9545 register targeted for transfer (where the first byte

to follow the data instruction is the most significant byte of the

data instruction, it knows to interpret the next two bytes as the

Note that the value of the register transfer instruction encodes

the payload length (number of bytes). That is, the EEPROM

controller knows how many register bytes to transfer to/from

the indicated register by adding 1 to the instruction value. For

example, Data Instruction 0x1A has a decimal value of 26;

therefore, the controller knows to transfer 27 bytes to and from

the target register (that is, one more than the value of the

instruction).

Input/Output Update Instruction (0x80)

When the EEPROM controller encounters an input/output

update instruction during an upload sequence, it stores the

instruction in EEPROM. When encountered during a download

sequence, however, the EEPROM controller initiates an

input/output update event (equivalent to the user asserting the

IO_UPDATE bit in the serial port section of the register map).

Device Action Instructions (0x90 to 0xAF)

When the EEPROM controller encounters a device action

instruction during an upload sequence, it stores the instruction

in EEPROM. When encountered during a download sequence,

however, the EEPROM controller executes the specified action

per Table 62.

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