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AD9545 Datasheet(PDF) 145 Page - Analog Devices |
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AD9545 Datasheet(HTML) 145 Page - Analog Devices |
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145 / 157 page  Data Sheet AD9545 Rev. A | Page 145 of 157 APPLICATIONS INFORMATION OPTICAL NETWORKING LINE CARD One example of an optical networking application appears in Figure 110, which shows a line card and optical module using direct timing. The AD9545 accepts redundant input clocks from two remote timing cards. The AD9545 has all of the necessary functionality to provide automatic switching between the two input clocks in the event either one of them fails. By employing PLL0 and PLL1 with both using the same input clock, the PLLs generate the necessary clock frequencies for the transmit (Tx) and receive (Rx) paths. Another optical networking example (see Figure 111) operates in loop timing mode typical of a WAN application. Similar to the direct timing mode, PLL0 uses one of the redundant input timing signals to generate clocks for the Tx path with the appropriate frequency translation ratio. With loop timing, however, the other PLL (PLL1) uses the recovered clock from the CDR as its input, suppresses the jitter commonly present in the Rx path, regenerates output clocks for the Rx path, and provides a reference clock to the central timing card via the backplane. FRAMER/FEC DESERIALIZER CDR POST AMP TIA PHOTO DIODE LDD LASER DIODE FIBER Rx FIBER Tx LINE CARD OPTICAL MODULE FROM TIMING CARD 1 FROM TIMING CARD 2 FRAMER/FEC SERIALIZER SYSTEM CLOCK PLL STATUS AND CONTROL PINS AD9545 TEMPERATURE SENSOR SYSTEM CLOCK COMPENSATION REFERENCE SWITCHING CONTROL REFERENCE MONITORS ÷R TDC REFA REFAA REFB REFBB REFERENCE INPUTS NCO DPLL DPLL0 APLL0 NCO DPLL DPLL1 PLL APLL1 VCO PLL0 PLL1 DISTRIBUTION OUTPUTS DISTRIBUTION OUTPUTS INTERNAL ZERO DELAY INTERNAL ZERO DELAY EEPROM (OPTIONAL) XOA/XOB SYSTEM CLOCK DIGITAL CROSS POINT MUX SERIAL PORT (SPI/I2C) AND EEPROM CONTROLLER M0 TO M6 AUXILIARY NCOs AUXILIARY TDCs OUT0AP/OUT0AN OUT0BP/OUT0BN OUT0CP/OUT0CN OUT1AP/OUT1AN OUT1BP/OUT1BN ÷2 ÷2 ÷Q ÷Q PLL VCO Figure 110. Optical Line Card Direct Timing Example POST AMP TIA PHOTO DIODE LDD LASER DIODE FIBER Rx FIBER Tx LINE CARD OPTICAL MODULE FROM TIMING CARD 1 FROM TIMING CARD 2 FRAMER/FEC SERIALIZER SYSTEM CLOCK PLL STATUS AND CONTROL PINS AD9545 TEMPERATURE SENSOR SYSTEM CLOCK COMPENSATION REFERENCE SWITCHING CONTROL REFERENCE MONITORS ÷R TDC REFA REFAA REFB REFBB REFERENCE INPUTS NCO DPLL DPLL0 APLL0 NCO DPLL DPLL1 PLL APLL1 VCO PLL0 PLL1 DISTRIBUTION OUTPUTS DISTRIBUTION OUTPUTS INTERNAL ZERO DELAY INTERNAL ZERO DELAY EEPROM (OPTIONAL) XOA/XOB SYSTEM CLOCK DIGITAL CROSS POINT MUX SERIAL PORT (SPI/I2C) AND EEPROM CONTROLLER M0 TO M6 AUXILIARY NCOs AUXILIARY TDCs OUT0AP/OUT0AN OUT0BP/OUT0BN OUT0CP/OUT0CN OUT1AP/OUT1AN OUT1BP/OUT1BN ÷2 ÷2 ÷Q ÷Q PLL VCO FRAMER/FEC DESERIALIZER CDR Figure 111. Optical Line Card Loop Timing Example |
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