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AD9545 Datasheet(PDF) 146 Page - Analog Devices |
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AD9545 Datasheet(HTML) 146 Page - Analog Devices |
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146 / 157 page  AD9545 Data Sheet Rev. A | Page 146 of 157 The AD9545 can also perform specialized frequency translation tasks to accommodate FEC and/or jitter suppression associated with a gapped clock scenario, as shown in Figure 110 and Figure 111. The flexibility and available feature set of the AD9545 enables it to meet the continually evolving nature of optical line card protocols and functions. However, the examples given Figure 110 and Figure 111 are by no means exhaustive. SMALL CELL BASE STATION The diagram shown in Figure 112 is an example of the AD9545 providing all of the synchronization necessary for the baseband unit of a small cell base station. The built-in JESD204B support enables a particularly compact and efficient design. The AD9545 can lock to any of the following input sources: • GPS • SyncE • IEEE1588 (requires a separate IEEE1588 servo and software stack—see Figure 113 for an example of using the AD9545 as part of an IEEE1588 servo loop) • Loop timed input (in the case of SONET/SDH backhaul) In this small cell application, PLL0 provides up to four device system reference (SYSREF) clocks for clocking wireless transceivers (such as the AD9371), a clock signal for distribution through a 1:4 buffer for clocking up to two radio cards and an optional CPU interface clock for the baseband processor. Independently, PLL1 provides a clock for the backhaul interface via the network connection. PLL0 and PLL1 derive their input timing from the appropriate input sources (GPS, IEEE1588, loop timing from the network, or SyncE). Because the AD9545 supports an optional EEPROM, the user can store the application configuration for automatic download at power-up. SMALL CELL 1:4 SYSREF TO RADIO 1 SYSREF TO RADIO 2 SYSREF TO BASEBAND BASEBAND PROCESSOR NETWORK CONNECTION RADIO (2 CARDS) <1PS <1PS EXTERNAL NETWORK EEPROM (OPTIONAL) SYSTEM CLOCK PLL STATUS AND CONTROL PINS AD9545 TEMPERATURE SENSOR SYSTEM CLOCK COMPENSATION REFERENCE SWITCHING CONTROL REFERENCE MONITORS ÷R TDC REFA REFAA REFB REFBB REFERENCE INPUTS NCO DPLL DPLL0 APLL0 NCO DPLL DPLL1 PLL APLL1 VCO PLL0 PLL1 DISTRIBUTION OUTPUTS DISTRIBUTION OUTPUTS INTERNAL ZERO DELAY INTERNAL ZERO DELAY XOA/XOB SYSTEM CLOCK DIGITAL CROSS POINT MUX SERIAL PORT (SPI/I2C) AND EEPROM CONTROLLER M0 TO M6 AUXILIARY NCOs AUXILIARY TDCs OUT0AP/OUT0AN OUT0BP/OUT0BN OUT0CP/OUT0CN OUT1AP/OUT1AN OUT1BP/OUT1BN ÷2 ÷2 ÷Q ÷Q PLL VCO INPUT GPS, IEEE1588, LOOP TIMED FROM NETWORK, SyncE ETHERNET SyncE PON SONET/SDH 30.72MHz 61.44MHz 122.88MHz JESD204B SUPPORT 30.72MHz 61.44MHz 122.88MHz 245.76MHz 307.2MHz DIFF/SE OUTPUTS 10MHz 25MHz 125MHz 156.25MHz 312.5MHz DIFF/SE OUTPUTS Figure 112. AD9545 Small Cell Application |
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