AD9545 datasheet(147/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 147 of 157

IEEE 1588 SERVO

The AD9545 provides all of the jitter cleaning, phase shifting,

and synchronization for an IEEE 1588 servo and software stack

in a Telecom-BC (T-BC) with hybrid support application (see

Figure 113). The diagram in Figure 113 supports IEEE 1588

master and slave clock operation.

PLL0 provides two filtered, 125 MHz SyncE clocks. PLL1

provides for two output clocks, each operating from 1 pps up to

500 MHz with high resolution output phase adjustment and

slew rate limiting capability, which allows filtering a GPS signal,

for example, and provides PTP asymmetry correction (with

appropriate PTP software support).

Figure 113 also shows the ability of the AD9545 to compensate

for system clock errors by taking advantage of a frequency stable

source applied at the reference input (REF IN) input and using

the auxiliary NCOs as references to PLL0 and PLL1. This

capability improves the overall timing precision of the system.

The performance and feature set of the AD9545 make it ideal

for enabling the latest IEEE 1588 features, as well as the latest

ITU-T packet synchronization related standards for 4G and 5G

wireless networks.

REF IN

1PPS TO 750 MHz

SYSTEM

CLOCK PLL

STATUS

AND CONTROL

PINS

AD9545

TEMPERATURE

SENSOR

SYSTEM CLOCK

COMPENSATION

REFERENCE

SWITCHING

CONTROL

REFERENCE

MONITORS

REFA

REFAA

REFB

REFBB

NCO

DPLL

DPLL0

APLL0

NCO

DPLL

DPLL1

PLL

APLL1

VCO

PLL0

PLL1

DISTRIBUTION

OUTPUTS

DISTRIBUTION

OUTPUTS

INTERNAL ZERO DELAY

XOA/XOB

SYSTEM

CLOCK

DIGITAL

CROSS

POINT

MUX

SERIAL PORT (SPI/I2C)

AND EEPROM

CONTROLLER

M0 TO M6

AUXILIARY

NCOs

AUXILIARY

TDCs

OUT0AP/OUT0AN

OUT0BP/OUT0BN

OUT0CP/OUT0CN

OUT1AP/OUT1AN

OUT1BP/OUT1BN

÷2

÷Q

PLL VCO

÷R

TDC

REFERENCE

INPUTS

MEMORY

CPU

MAC

PACKET

CLASSIFIER

AND

TIMESTAMP

TIME

DAY

CLOCK INTERFACES

MANAGEMENT

INTERFACE

RGMII/SGMII

(WITH SyncE SUPPORT)

TIME OF DAY

IN/OUT

(1PPS + TUART WITH

NEMA FORMAT)

CLOCK OUT

1PPS TO 500 MHz

(WITH OPTIONAL

1PPS MODULATION)

125MHz FILTERED/ADJUSTED

1PPS

Figure 113. Using an AD9545 in an IEEE1588 Version 2 Application

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